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| MM74C925 * MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers October 1987 Revised January 2004 MM74C925 * MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers General Description The MM74C925 and MM74C926 CMOS counters consist of a 4-digit counter, an internal output latch, NPN output sourcing drivers for a 7-segment display, and an internal multiplexing circuitry with four multiplexing outputs. The multiplexing circuit has its own free-running oscillator, and requires no external clock. The counters advance on negative edge of clock. A HIGH signal on the Reset input will reset the counter to zero, and reset the carry-out LOW. A LOW signal on the Latch Enable input will latch the number in the counters into the internal output latches. A HIGH signal on Display Select input will select the number in the counter to be displayed; a LOW level signal on the Display Select will select the number in the output latch to be displayed. The MM74C925 is a 4-decade counter and has Latch Enable, Clock and Reset inputs. The MM74C926 is like the MM74C925 except that it has a display select and a carry-out used for cascading counters. The carry-out signal goes HIGH at 6000, goes back LOW at 0000. Features s Wide supply voltage range: 3V to 6V s Guaranteed noise margin: 1V s High noise immunity: 0.45 VCC (typ.) s High segment sourcing current: 40 mA @ VCC - 1.6V, VCC = 5V s Internal multiplexing circuitry Design Considerations Segment resistors are desirable to minimize power dissipation and chip heating. The DS75492 serves as a good digit driver when it is desired to drive bright displays. When using this driver with a 5V supply at room temperature, the display can be driven without segment resistors to full illumination. The user must use caution in this mode however, to prevent overheating of the device by using too high a supply voltage or by operating at high ambient temperatures. The input protection circuitry consists of a series resistor, and a diode to ground. Thus input signals exceeding VCC will not be clamped. This input signal should not be allowed to exceed 15V. Ordering Code: Order Number MM74C925N MM74C926N Package Number N16E N18B Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagrams Pin Assignments for DIP Top View MM74C925 Top View MM74C926 DS005919 www.fairchildsemi.com (c) 2004 Fairchild Semiconductor Corporation MM74C925 * MM74C926 Functional Description Reset -- Asynchronous, active high Low, displays output of latch Latch Enable -- High, flow through condition Low, latch condition Clock --Negative edge sensitive Display Select -- High, displays output of counter Segment Output -- Current sourcing with 40 mA @VOUT = VCC - 1.6V (typ.) Also, sink capability = 2 LTTL loads Digit Output -- Current sourcing with 1 mA @VOUT = 1.75V. Also, sink capability = 2 LTTL loads Carry-Out -- 2 LTTL loads. See carry-out waveforms. Logic Diagrams MM74C925 MM74C926 www.fairchildsemi.com 2 MM74C925 * MM74C926 Absolute Maximum Ratings(Note 1) Voltage at Any Output Pin Voltage at Any Input Pin Operating Temperature Range (TA) Storage Temperature Range Power Dissipation (PD) Operating VCC Range VCC Lead Temperature (Soldering, 10 seconds) 260C GND - 0.3V to VCC + 0.3V GND - 0.3V to +15V -40C to +85C -65C to +150C Refer to PD(MAX) vs TA Graph 3V to 6V 6.5V Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply at -40C tj + 85C, unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage (Carry-Out and Digit Output Only) Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current VCC = 5V, IO = 10 A VCC = 5V, VIN = 15V VCC = 5V, VIN = 0V VCC = 5V, Outputs Open Circuit, VIN = 0V or 5V CMOS/LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) VOUT Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage (Carry-Out and Digit Output Only) Logical "0" Output Voltage Output Voltage (Segment Sourcing Output) RON Output Resistance (Segment Sourcing Output) Output Resistance (Segment Output) Temperature Coefficient ISOURCE ISOURCE ISINK jA Output Source Current (Digit Output) Output Source Current (Carry-Out) Output Sink Current (All Outputs) Thermal Resistance MM74C925: (Note 2) MM74C926 Note 2: jA measured in free-air with device soldered into printed circuit board. Parameter VCC = 5V VCC = 5V Conditions Min 3.5 Typ Max Units V 1.5 4.5 0.5 0.005 -1 -0.005 20 1000 1 V V V A A A VCC = 5V, IO = -10 A VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = 360 A IOUT = -65 mA, VCC = 5V, Tj = 25C IOUT = -40 mA, VCC = 5V Tj = 100C Tj = 150C IOUT = -65 mA, VCC = 5V, Tj = 25C IOUT = -40 mA, VCC = 5V Tj = 100C Tj = 150C VCC - 2 0.8 2.4 0.4 VCC - 2 VCC - 1.6 VCC - 2 VCC - 1.3 VCC - 1.2 VCC - 1.4 20 30 35 0.6 32 40 50 0.8 V V V V V V V %/C mA mA mA 100 90 C/W C/W OUTPUT DRIVE VCC = 4.75V, VOUT = 1.75V, Tj = 150C VCC = 5V, VOUT = 0V, Tj = 25C VCC = 5V, VOUT = VCC, Tj = 25C -1 -1.75 1.75 -2 -3.3 3.6 75 70 3 www.fairchildsemi.com MM74C925 * MM74C926 AC Electrical Characteristics TA = 25C, CL = 50 pF, unless otherwise noted Symbol fMAX tr, tf tWR tWLE Parameter Maximum Clock Frequency Maximum Clock Rise or Fall Time Reset Pulse Width Latch Enable Pulse Width (Note 3) Conditions Min 2 1.5 250 320 250 320 2500 3200 0 0 320 400 1000 5 Typ 4 3 15 Tj = 25C Tj = 100C Tj = 25C Tj = 100C Tj = 25C Tj = 100C Tj = 25C Tj = 100C Tj = 25C Tj = 100C 100 125 100 125 1250 1600 -100 -100 160 200 Max Units MHz MHz s ns ns ns ns ns ns ns ns ns ns Hz pF VCC = 5V, VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V Any Input (Note 4) Tj = 25C Square Wave Clock Tj = 100C tSET(CK, LE) Clock to Latch Enable Set-Up Time tLR tSET(R, LE) fMUX CIN Latch Enable to Reset Wait Time Reset to Latch Enable Set-Up Time Multiplexing Output Frequency Input Capacitance Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Typical Performance Characteristics Typical Segment Current vs Output Voltage Maximum Power Dissipation vs Ambient Temperature Note: VD = Voltage across digit driver Typical Average Segment Current vs Segment Resistor Value www.fairchildsemi.com 4 MM74C925 * MM74C926 Typical Performance Characteristics Segment Output Driver (Continued) Input Protection Common Cathode LED Display Segment Identification 5 www.fairchildsemi.com MM74C925 * MM74C926 Switching Time Waveforms Input Waveforms Multiplexing Output Waveforms T = 1/fMUX Carry-Out Waveforms www.fairchildsemi.com 6 MM74C925 * MM74C926 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E 7 www.fairchildsemi.com MM74C925 * MM74C926 4-Digit Counters with Multiplexed 7-Segment Output Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N18B Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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